377 lines
8.7 KiB
C++
377 lines
8.7 KiB
C++
#ifndef ADDRESSSPACE_HPP
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#define ADDRESSSPACE_HPP
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#include <fstream>
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#include <filesystem>
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#include <cstdint>
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#include <cstring>
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#include <string>
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#include <vector>
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#include "defines.hpp"
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class AddressSpace {
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bool bootromLoaded = true;
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Byte bootrom[BOOTROM_SIZE] = {0};
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std::vector<Byte> game;
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bool testing;
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Byte testRam[0xFFFF];
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Byte* cartridgeRam = nullptr;
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public:
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AddressSpace() {
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// Initialize the memory to zero
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memoryLayout = {};
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}
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struct {
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Byte* romBank0; //[ROM_BANK_SIZE] Mapped to 0x0000
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Byte* romBankSwitch; //[ROM_BANK_SIZE] Mapped to 0x4000
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Byte vram[0x2000]; //Mapped to 0x8000
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Byte* externalRam; //[0x2000]; Mapped to 0xA000
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Byte memoryBank1[0x1000]; //Mapped to 0xC000
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Byte memoryBank2[0x1000]; //Mapped to 0xD000
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Byte oam[0xA0]; //Mapped to 0xFE00
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Byte notUsable[0x60]; //Mapped to 0xFEA0
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//General purpose hardware registers
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Byte JOYP;
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Byte SB;
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Byte SC;
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Byte DIV;
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//Timer registers
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Byte TIMA;
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Byte TMA;
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Byte TAC = 0xF8;
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//interrupt flag and enable
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Byte IF = 0xE1;;
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//Sound registers
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Byte NR10;
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Byte NR11;
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Byte NR12;
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Byte NR13;
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Byte NR14;
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Byte NR20; //not used
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Byte NR21;
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Byte NR22;
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Byte NR23;
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Byte NR24;
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Byte NR30;
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Byte NR31;
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Byte NR32;
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Byte NR33;
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Byte NR34;
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Byte NR40; //unused
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Byte NR41;
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Byte NR42;
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Byte NR43;
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Byte NR44;
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Byte NR50;
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Byte NR51;
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Byte NR52;
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Byte waveRam[0x10];
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//PPU registers
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Byte LCDC;
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Byte STAT;
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Byte SCY;
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Byte SCX;
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Byte LY;
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Byte LYC;
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Byte DMA;
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Byte BGP;
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Byte OBP0;
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Byte OBP1;
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Byte WY;
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Byte WX;
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Byte specialRam[0x7F]; //Mapped to 0xFF80
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Byte IE; // Mapped to 0xFFFF
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} memoryLayout{};
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void unmapBootrom();
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void mapBootrom();
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bool getBootromState() const;
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void loadBootrom(const std::string& filename);
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void loadGame(const std::string& filename);
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void determineMBCInfo();
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static bool testMBCWrite(Word address);
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Byte* MBCRead(Word address);
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//prevents seg faults when programs with no MBC try to write to ROM
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Byte dummyVal = 0;
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void MBCUpdate();
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void loadRomBank();
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void createRamBank();
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void loadRamBank();
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MBCType MBC = {};
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uint32_t romSize = 0;
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uint32_t romBanks = 0;
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uint32_t externalRamSize = 0;
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uint32_t externalRamBanks = 0;
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//Selected ROM Bank = (Secondary Bank << 5) + ROM Bank
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Byte selectedRomBank = 0;
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Byte romBankRegister = 0x00;
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//2 bit register acts as secondary rom bank register or ram bank number
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Byte twoBitBankRegister = 0x0;
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Byte selectedExternalRamBank = 0;
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Byte romRamSelect = 0x00;
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Byte ramEnable = 0x00;
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//MBC3
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Byte latchClockData = 0x00;
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Byte ramBankRTCRegister = 0x00;
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void setTesting(bool state);
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//read
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Byte operator[](const Word address) const {
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if (testing)
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return testRam[address];
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if (address < 0x0100 && bootromLoaded)
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return bootrom[address];
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if (address < 0x4000)
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return memoryLayout.romBank0[address];
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if (address < 0x8000)
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return memoryLayout.romBankSwitch[address - 0x4000];
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if (address < 0xA000)
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return memoryLayout.vram[address - 0x8000];
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if (address < 0xC000) {
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if (externalRamSize == 0)
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return 0xFF;
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return memoryLayout.externalRam[address - 0xA000];
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}
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if (address < 0xD000)
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return memoryLayout.memoryBank1[address - 0xC000];
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if (address < 0xE000)
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return memoryLayout.memoryBank2[address - 0xD000];
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if (address < 0xFE00)
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return memoryLayout.memoryBank1[address - 0xE000];
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if (address < 0xFEA0)
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return memoryLayout.oam[address - 0xFE00];
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if (address < 0xFF00) {
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if ((memoryLayout.STAT & 0x03) == 2 || (memoryLayout.STAT & 0x03) == 3)
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return 0xFF;
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return 0x00;
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}
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if (address < 0xFF80)
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switch (address) {
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case 0xFF00:
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return memoryLayout.JOYP;
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case 0xFF01:
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return memoryLayout.SB;
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case 0xFF02:
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return memoryLayout.SC;
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case 0xFF04:
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return memoryLayout.DIV;
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case 0xFF05:
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return memoryLayout.TIMA;
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case 0xFF06:
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return memoryLayout.TMA;
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case 0xFF07:
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return memoryLayout.TAC | 0xF8;;
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case 0xFF0F:
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return memoryLayout.IF | 0xE0;
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case 0xFF10:
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return memoryLayout.NR10;
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case 0xFF11:
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return memoryLayout.NR11;
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case 0xFF12:
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return memoryLayout.NR12;
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case 0xFF13:
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return memoryLayout.NR13;
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case 0xFF14:
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return memoryLayout.NR14;
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case 0xFF16:
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return memoryLayout.NR21;
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case 0xFF17:
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return memoryLayout.NR22;
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case 0xFF18:
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return memoryLayout.NR23;
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case 0xFF19:
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return memoryLayout.NR24;
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case 0xFF1A:
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return memoryLayout.NR30;
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case 0xFF1B:
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return memoryLayout.NR31;
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case 0xFF1C:
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return memoryLayout.NR32;
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case 0xFF1D:
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return memoryLayout.NR33;
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case 0xFF1E:
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return memoryLayout.NR34;
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case 0xFF20:
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return memoryLayout.NR41;
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case 0xFF21:
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return memoryLayout.NR42;
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case 0xFF22:
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return memoryLayout.NR43;
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case 0xFF23:
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return memoryLayout.NR44;
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case 0xFF24:
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return memoryLayout.NR50;
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case 0xFF25:
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return memoryLayout.NR51;
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case 0xFF26:
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return memoryLayout.NR52;
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// PPU registers
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case 0xFF40:
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return memoryLayout.LCDC;
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case 0xFF41:
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return memoryLayout.STAT;
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case 0xFF42:
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return memoryLayout.SCY;
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case 0xFF43:
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return memoryLayout.SCX;
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case 0xFF44:
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//for debugging only
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//return 0x90;
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return memoryLayout.LY;
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case 0xFF45:
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return memoryLayout.LYC;
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case 0xFF46:
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return memoryLayout.DMA;
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case 0xFF47:
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return memoryLayout.BGP;
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case 0xFF48:
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return memoryLayout.OBP0;
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case 0xFF49:
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return memoryLayout.OBP1;
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case 0xFF4A:
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return memoryLayout.WY;
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case 0xFF4B:
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return memoryLayout.WX;
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default:
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if (address >= 0xFF30 && address <= 0xFF3F) {
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return memoryLayout.waveRam[address - 0xFF30];
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}
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return 0xFF;
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}
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if (address < 0xFFFF)
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return memoryLayout.specialRam[address - 0xFF80];
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//0xFFFF
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return memoryLayout.IE;
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}
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//write
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Byte& operator[](const Word address) {
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dummyVal = 0xFF;
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if (testing)
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return testRam[address];
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if (address < 0x0100 && bootromLoaded)
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return bootrom[address];
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if (address < 0x8000)
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return (*MBCRead(address));
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if (address < 0xA000)
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return memoryLayout.vram[address - 0x8000];
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if (address < 0xC000)
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return memoryLayout.externalRam[address - 0xA000];
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if (address < 0xD000)
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return memoryLayout.memoryBank1[address - 0xC000];
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if (address < 0xE000)
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return memoryLayout.memoryBank2[address - 0xD000];
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if (address < 0xFE00)
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return memoryLayout.memoryBank1[address - 0xE000];
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if (address < 0xFEA0)
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return memoryLayout.oam[address - 0xFE00];
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if (address < 0xFF00)
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return memoryLayout.notUsable[address - 0xFEA0];
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if (address < 0xFF80)
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switch (address) {
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case 0xFF00:
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return memoryLayout.JOYP;
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case 0xFF01:
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return memoryLayout.SB;
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case 0xFF02:
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return memoryLayout.SC;
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case 0xFF04:
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memoryLayout.DIV = 0;
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return dummyVal;
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// Timer registers
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case 0xFF05:
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return memoryLayout.TIMA;
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case 0xFF06:
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return memoryLayout.TMA;
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case 0xFF07:
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return memoryLayout.TAC;
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case 0xFF0F:
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return memoryLayout.IF;
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case 0xFF10:
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return memoryLayout.NR10;
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case 0xFF11:
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return memoryLayout.NR11;
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case 0xFF12:
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return memoryLayout.NR12;
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case 0xFF13:
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return memoryLayout.NR13;
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case 0xFF14:
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return memoryLayout.NR14;
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case 0xFF16:
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return memoryLayout.NR21;
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case 0xFF17:
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return memoryLayout.NR22;
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case 0xFF18:
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return memoryLayout.NR23;
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case 0xFF19:
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return memoryLayout.NR24;
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case 0xFF1A:
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return memoryLayout.NR30;
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case 0xFF1B:
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return memoryLayout.NR31;
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case 0xFF1C:
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return memoryLayout.NR32;
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case 0xFF1D:
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return memoryLayout.NR33;
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case 0xFF1E:
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return memoryLayout.NR34;
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case 0xFF20:
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return memoryLayout.NR41;
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case 0xFF21:
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return memoryLayout.NR42;
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case 0xFF22:
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return memoryLayout.NR43;
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case 0xFF23:
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return memoryLayout.NR44;
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case 0xFF24:
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return memoryLayout.NR50;
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case 0xFF25:
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return memoryLayout.NR51;
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case 0xFF26:
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return memoryLayout.NR52;
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case 0xFF40:
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return memoryLayout.LCDC;
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case 0xFF41:
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return memoryLayout.STAT;
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case 0xFF42:
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return memoryLayout.SCY;
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case 0xFF43:
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return memoryLayout.SCX;
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case 0xFF44:
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dummyVal = memoryLayout.LY;
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return dummyVal;
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case 0xFF45:
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return memoryLayout.LYC;
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case 0xFF46:
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return memoryLayout.DMA;
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case 0xFF47:
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return memoryLayout.BGP;
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case 0xFF48:
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return memoryLayout.OBP0;
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case 0xFF49:
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return memoryLayout.OBP1;
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case 0xFF4A:
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return memoryLayout.WY;
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case 0xFF4B:
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return memoryLayout.WX;
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default:
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if (address >= 0xFF30 && address <= 0xFF3F) {
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return memoryLayout.waveRam[address - 0xFF30];
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}
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return dummyVal;
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}
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if (address < 0xFFFF)
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return memoryLayout.specialRam[address - 0xFF80];
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//0xFFFF
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return memoryLayout.IE;
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}
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};
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#endif //ADDRESSSPACE_HPP
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